The present invention relates to an apparatus for testing a semiconductor memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory or similar memory. More particularly, the present invention is directed to, but not exclusively limited to, a memory testing apparatus which is capable of concurrently testing a plurality of semiconductor flash memories in parallel.
FIG. 1 is a block diagram showing the basic construction of a conventional semiconductor memory test apparatus. The semiconductor memory test apparatus comprises a timing generator 10, pattern generator 2, a waveform shaper 3, a drivers DR, a logical comparing part 40, and a fail analyzing memory 5. The semiconductor memory test apparatus tests a memory under test MUT (hereinafter the memory under MUT is referred to as simply test memory MUT). When the semiconductor memory test apparatus is used only for determining whether a semiconductor memory is normal/abnormal (PASS/FAIL), the fail analyzing memory 5 may not be used.
The pattern generator 2 outputs an address signal ADRS, a test data signal TPD, and a control signal CS to the test memory MUT in accordance with a basic clock CK generated by the timing generator 10. These signals are supplied to the waveform shaper 3. These signals are shaped to logical waveforms necessary for the test and the voltage thereof is raised by the driver DR. The resultant signals are applied to the test memory MUT.
With the control signal CS, the test data signal TPD is written to and read from the test memory MUT. The test data signal RD read from the test memory MUT is supplied to a logical comparing part 40. The logical comparing part 40 compares expected data ED output from the pattern generator 2 with the test data RD being read. Depending on whether or not the expected data ED matches with the test data RD, it is determined whether the test memory MUT is good or no good (PASS or FALL).
When a mismatch is detected, the logical comparing part 40 supplies a fail signal to a fail analyzing memory 5. The fail information is stored in a memory cell of the fail analyzing memory 5, the memory cell being designated with an address signal ADRS generated by the pattern generator 2. After the test is completed, the content stored in the fail analyzing memory 5 is analyzed.
In a conventional fabrication line, n test memories MUT.sub.1 to MUT.sub.n are tested in parallel on n test channels so as to improve test efficiency.
Next, the flash memory will be described.
In recent years, the flash memory is a non-volatile memory having a gained attention by those in the art. The flash memory has large storage capacity and data stored therein can be rewritten many times. However, due to the construction of the flash memory, with one write operation, data cannot be always successfully written so each address. Thus, normally, the write operation should be repeated several times. The number of times of the write operation required depends on the type of the test memory MUT. In addition, even if the type of the test memory MUT is the same, the number of times of the write operation required depends on each address thereof. In the data write test for the flash memory, when data have been written to all required memory cells within a predetermined number of times, it is determined that the memory is good. In the data erase test for the flash memory, when data have been erased from all required memory cells within a predetermined number of times, it is determined that the memory is good.
FIG. 2 shows the construction of the logical comparing part 40 having n test channels. The logical comparing part 40 comprises a plurality of logical comparators 4.sub.1 to 4.sub.n and an allpass detector 43. The logical comparators 4.sub.1 to 4.sub.n receive data RD from the test memories MUT.sub.1 to MUT.sub.n and logically compare the data RD with expected data ED. The allpass detector 43 is constructed of an NOR gate. In this example, in each of the logical comparators 4.sub.1 to 4n.sub.n a mismatch detecting circuit 4X that is constructed of an XOR gate compares analog logical determined result with the expected data ED at the timing of strobe STRB of input data. When the compared result is match (PASS), the circuit 4X outputs "0". When the compared result is mismatch (FAIL), the circuit 4X outputs "1". The logical comparators 4.sub.1 to 4.sub.n supply the compared results that are FAIL/PASS status data (or simply, F/P data) to the fail analyzing memory 5 and the allpass detector 43. The allpass detector 43 outputs a match flag MF representing "1" to the pattern generator 2.
When a plurality of flash memories are tested in parallel at the same time, if the read data RD at a particular address of all the test flash memories MUT.sub.1 to MUT.sub.n matches with the expected data ED, the match flag MF takes place. With the match flag MF, the pattern generator 2 outputs expected data of the next address. When the expected data does not match with the read data of the test flash memories MUT.sub.1 to MUT.sub.n the data write test (or data erase test) is performed at the same address. (In the following description, only the data write test will be explained.) When the data write test is repeated a predetermined number of times, if the expected data does not match with the read data of the test flash memories MUT.sub.1 to MUT.sub.n, the flow jumps to another process routine and stores data representing that the test flash memory MUT is FAIL to a corresponding address of the fail analyzing memory 5.
However, the flash memory has excessively write inhibition characteristic where data cannot be excessively written to an address where data has been successfully written. Thus, when a plurality of flash memories MUT.sub.1 to MUT.sub.n are attempted to be tested in parallel at the same time, as described above, the number of times of data write operation required depends on each flash memory MUT. Thus, if the data write operation is performed for a flash memory MUT where data has not been successfully written, the same operation is also executed for other flash memories MUT where the data write operation has been successfully performed. Consequently, such an attempt violates the excessively write inhibition characteristic of the flash memories MUT. This requirement applies to the data erase test.
As a result, so far, a plurality of flash memories could not be tested in parallel at the same time.